Ars Technica

Cache and memory in the many-core era

One of the greatest challenges facing the designers of many-core processors is resource contention. The chart below visually lays out the problem of resource contention, but for most of us the idea is ...
Hackaday

Spectre And Meltdown: How Cache Works

The year so far has been filled with news of Spectre and Meltdown. These exploits take advantage of features like speculative execution, and memory access timing. What they have in common is the fact ...
EDN

Efficient checks for cache-coherency verification in complex SoCs

Cache, in its crude definition, is a faster memory which stores copies of data from frequently used main memory locations. Nowadays, multiprocessor systems are supporting shared memories in hardware, ...
TechRepublic

CAMEO:A Two-Level Memory Organization with Capacity of Main Memory and Flexibility of Hardware-Managed Cache

In this paper, the authors analyze the trade-offs in architecting stacked DRAM either as part of main memory or as a hardware-managed cache. Using stacked DRAM as part of main memory increases the ...
Electronic Design

Hardware Compression Works at the Memory Cache Level

How lossless data compression can reduce memory and power requirements. How ZeroPoint’s compression technology differs from the competition. One can never have enough memory, and one way to get more ...
Business Wire

Everspin ST-MRAM Incorporated for Cache Memory Into Buffalo Memory SSD

CHANDLER, Ariz.--(BUSINESS WIRE)--Everspin Technologies today announced that Buffalo Memory is introducing a new industrial SATA III SSD that incorporates Everspin’s Spin-Torque MRAM (ST-MRAM) as ...